1. Field of the Invention
The present invention relates to an MOSC and an operating method thereof. More particularly, the present invention relates to an MOSC that has a low power loss and having a comparatively simple logic control module and a simple operating method.
2. Description of Related Art
Along with the rapid development in the diversification of function of electronic products, the electronic product manufacturers generally adopt integrated circuits (ICs) of different specifications in the products of their own, so as to meet various requirements. However, as the operating voltage of the ICs adopted is different, the electronic product manufacturers adopt an MOSC in the electronic products to convert a fixed voltage into various voltage levels for the ICs, such as the circuits in FIGS. 1 and 2, having different operating voltages.
FIG. 1 is a conventional MOSC. Referring to FIG. 1, the conventional MOSC includes a logic controller 101, PMOS transistors 102 and 103, an NMOS transistor 104, a cell 105, and an inductor 106. When the transistor 104 is on and the transistors 102, 103 are off under the control of the logic controller 101, the electric power stored in the cell 105 is discharged to a ground voltage GND via the inductor 106 and the transistor 104, thereby some energy is stored in the inductor 106. Then, the transistors 103, 104 are off and the transistor 102 is on under the control of the logic controller 101, such that the electric power stored in the cell 105 and the energy stored in the inductor 106 are transmitted to an output terminal VDD1 of the MOSC via the transistor 102, so as to provide a voltage to the circuit coupled to the output terminal VDD1.
After that, the transistors 102, 103 are off and the transistor 104 is on under the control of the logic controller 101, such that the electric power stored in the cell 105 is discharged to the ground voltage GND via the inductor 106 and the transistor 104, thereby some energy is stored in the inductor 106. Then, the transistors 102, 104 are off and the transistor 103 is on under the control of the logic controller 101, such that the electric power stored in the cell 105 and the energy stored in the inductor 106 are transmitted to an output terminal VDD2 of the MOSC via the transistor 103, so as to provide a voltage to the circuit coupled to the output terminal VDD2.
The energy stored in the inductor 106 varies with the on-time of the transistor 104, and thus controlling the on-time of the transistor 104 functions as controlling the amount of energy stored in the inductor 106. Therefore, the magnitude of the voltage at the output terminals VDD1, VDD2 can be controlled by controlling the amount of energy stored in the inductor 106.
However, when the output terminal VDD1 is used to output a voltage higher than the voltage output by the terminal VDD2, the design of coupling the well 107 of the transistor 103 to the output terminal VDD1 in the circuit as shown in FIG. 1 is improper, because this scheme may cause a body effect of the transistor 103, leading to the rising of the on-resistance of the transistor 103, and thus the transistor 103 has a higher power consumption and requires more time to be turned on. On the contrary, when the output terminal VDD2 is used to output a voltage higher than the voltage output by the output terminal VDD1, the transistor 102 may has the same situation.
FIG. 2 is a conventional MOSC disclosed in U.S. Pat. No. 6,853,171B2. Referring to FIG. 2, the circuit includes a regulation module 201, PMOS transistors 202 and 203, an NMOS transistor 204, a logic control module 205, a cell 206, an inductor 207, and capacitors 208 and 209. The output terminal VDD1 as shown in FIG. 2 is used to output a voltage higher than the voltage output by the output terminal VDD2.
The difference between the circuit of FIG. 2 and that in FIG. 1 is described as follows. The on and off of the transistors 202, 203, 204 in FIG. 2 are controlled according to a signal output by the regulation module 201, and the logic control module 205 in FIG. 2 controls the voltage of the gate and the well of the transistor 203 in the following manner. When the transistor 202 is on and the transistors 203, 204 are off, the gate and the well of the transistor 203 are coupled to the output terminal VDD1. When a voltage is output via the output terminal VDD2, a low logic signal (i.e., low level) is output to the gate of the transistor 203 to turn on the transistor 203 and couple the well of the transistor 203 to the output terminal VDD2. When the transistor 204 is on and the transistors 202, 203 are off, the gate and the well of the transistor 203 are coupled to the output terminal VDD2.
However, though in the above control scheme of the logic control module 205, the transistor 203 can act correctly when both are being turned on and turned off by controlling the voltage of the well and avoid the leakage current of the transistor 203, the complexity in controlling the logic control module 205 increases, which increases the difficulty in designing the logic control module 205. In addition, along with the increasing of complexity in control, the logic control module 205 must have a complicated circuit, such that the product is cost increased, and the profit margin of the manufacturer and the competitive capability of the product are reduced.